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[ SPEC No. 1 E
ISSUE:
L08 8 1 32 Aug. 29. 1996
1
SPECIFICATIONS
Product Type 5 V Drive 240 Outputs TFT-LCD Source Driver'
Model
No.
LH1684F
Kl'his specifications contains 34 pages including the cover and appendix. If you have any objections,please contact us before issuing purchasing order.
CUSTOMERS ACCEPTANCE DATE:
BY:PRESENTED
Y. SHIOTAw
Dept. General Manager
REVIEWED BY:
PREPARED BY:
,_ ---. - ._ ;*
ENGINEERING DEPARTMENT ! ..-LOGIC IC ENGINEERING CENTER SHARP CORPORATION `-;
._
- -___.
.
,
TENRIINTEGRATED CIRCUITS(I0 GRQUP7'::
---."
SHARP
LH1684F
GHandIe this document carefully for it contains material protected by international copyright law. Any reproduction , full or in part , of this material is prohibited without the express written permission of the company. OWhen using the produc?s covered herein , please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be iiable for any damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2) , even for the following application areas , be sure to observe the precautions given in Paragraph (2) . Never use the products for the equipment listed in Paragraph (3) . * Office electronics - Instrumentation and measuring equipment * Machine tools * Audiovisual equipment * Home appliances * Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation , redundancy , and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes , trains , automobiles, and other transportation equipment - Mainframe computers - Traffic control systems - Gas leak detectors and automatic cutoff devices * Rescue and security equipment - Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality , reliability , or accuracy. - Aerospace equipment + Communications equipment for trunk lines * Control equipment for the nuclear power industry - Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation Paragraphs to a sales representative of the company. of the above three
OPlease direct all queries regarding the products covered herein to a sales representative company.
of the
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LH1684F
Contents
1. 2. 3. 4. 5.
Summary . . .. . . . . .. . .. . . . . .. . . . . .._..................................................................... Features
2
.. . . .. . . . .. . . .. . . .. . . . . . .. . . . . .. . . . . .. . . . . . . .. . . . . .. . . . .. .. . .. . .. . . . .. . . .. . . .. .. . . .. . . . . . .. . . .. . 2 .. . . ..._........................_............................................_..... 2 3 4 4 5 6 6 7 11 12 16 20
Pin Configuration
Block Diagram . .. . . . .. . . .. .._.__..___.....___._.._..._........_....................................... Description of Pins ................................................................................. 5.1 Designation of pins ....................................................................... 5.2 Input/output circuit types ............................................................... Description of Functions and Operations .................................................. 6.1 Functions of pin ............................................................................ 6.2 Operation of function .................................................................... 6.3 Outline of operation timing ........................................................... Timing chart for normal sampling operation .................................... 6.4 6.5 Timing chart for 3-point simultaneous sampling operation.. ............ 6.6 Precautions.. ..............................................................................
6.
7. 8. 9.
Absolute Maximum Ratings . . . . .. .. . . .. . . . . . . . .. . . . .. . . . . . .. . . .. . . .. . . .. . . . .. . . .. . . . . . .. . . . .. . 21 Recommended Operating Conditions . . . . . .. . . . . .. . . . . .. .. .. . .. . . .. . . . .. . . . .. . . . . . .. . . . . 21 21 21 .22 .23
Electrical Characteristics ........................................................................ 9.1 DC characteristics ........................................................................ 9.2 AC characteristics ....................................................................... 9.3 Timing diagram ........................................................................... Example of System Configuration Example of Typical Characteristics Package and Packing Specification
10. 1 1.. 12.
. .. . . . . . . .. . . . . .. . . . . . .. . . .. . .. . . .. . . . .. . . . .. . . . . .. . . . . .. . 24 .. . . . . . .. .. . . . . .. . . . . .. . . .. . .. . . .. . . . . .. . . . .. . . . . .. . . . . .. 25 . . . .. .. . . . . .. . . . . .. . . . .. . . .. . .. . . . .. . . . .. . . . . .. . . . .. . . . 26
SHARP
LH1684F 1. Summary
2
The LH1684F is a source driverforthe TFT liquid crystal panel used for LCD unit such as aTV set and has 240 LCD drive outputs. The LH1684F samples and holds three video signalsof R, G, and B by the sample and hold circuits at the synchronized with the clock CK , and output simultaneously the output voltage from all output pins.
2. Features
. No. of LCD drive outputs : . Supply voltage : * Output amplitude voltage : +Sampling frequency : +Video signals sampling : * Sampling timing :
240 outputs
4.5to5.5v
4.0 VP-P (at 5.0 V supply voltage)
2 0 MHz (MAX)
Shift direction can be selected.
(OS 1 OS240 or OS240 OS 1)
Normalsampling operation and 3-point simultaneous sampling operation can be selected. Compatible to stripe pixel array panels and delta pixel array panels * Video signal setting : by mode setting circuit. Max. 4 cascades (Internal counting system) . Cascade connection : * Package: 263 pinsTCP (Tape Carrier Package) CMOS silicon gate (p-type silicon substrate) * Process configuration : - Not designed or rated as radiation hardened.
3
Pin
Configuration
(Does
not
prescribeTCP
outline)
5 Dummy Pi0
$j?5Dummy pins ;5 _-.-----__----__--_-____________________--------------------------------- s:
On
Notes: 1. This TCP has 14 dummy pins which are not electrically connected. 2. The above pin configuration shows the pins asseen from the TCP surface.
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LH 1684F
4. Block Diagram Numerals in circles indicate the pin number.
3
1
Bkdirectional shift
RL CSl cs2 TST TSTl TST2 TST3
Control logic
............................ , 6 --_-_-_-____------_-vcc
GND OS1 . .. .. .. .. .. .. .. . .. .. . .. .. . OS240
Block name Control logic Bi-directional shift register
I Block function i I Used to create signals necessary for controlling cascade sequence ' and for discharge signal and sampling signals creation circuits, etc. ~Used as transfer circuit of video sampling start signals. ' It is possible to set the direction of sampling start signals sequence / by setting the FVL pin, from OS1 to OS240 or from OS240 to OS1 . Used to create the sampling signals corresponding j pin based on the sampling start signals transferred i directional shift register. to each output by the bi-
Sampling signal creation circuit
Mode setting circuit Sample and hold circuit
/ Used to set the form of the video signals to be sent to the sample 1and hold circuits. Used to sample the video signals input from the mode setting circuit I I : at the timing of the sampling signals and hold the sampling datas I until the next sampling operation. i The circuit comprises an operational amplifier and an output buffer 1and outputs the voltage corresponding to the data held in the / sample and hold circuit. i I
Output circuit
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LH 1684F
5. Description of Pins of pins Pinsymbol TSTl TST2 TST3 TST4 ' 1 1 ' ~ / : vcc GND SP CK CTR TST SAM RL CSl ' ' I cs2 Vbl Vb2 MODE TST5 VA : i VB vc / I / I/O 0 / / j ~ /i/I j / j ! : I ~ 1 1 j I I I I I I I I I I I I I I I I I I LCD drive output pins LSI test pin LSI test pin LSI test pin LSI test pin Power supply pins GNDpins Horizontal scanning start pulse input pin Horizontal shift clock input pin Analog circuit operation selecting pin LSI test pin Sampling mode selecting pin Sampling sequence Cascade sequence selecting pin setting pin 1 . I I I I I I / / / I Designation j Remarks I I
i
5.1 Designation Pin No. 1 to 240 241 242 1 243 244 245,263 246,262 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 I j j (
/ OS1 to OS240
Cascade sequence setting pin 2 , Bias voltage setting pin for output operational amplifiers ' / Bias voltage setting pin for output buffers Video signals form setting pin LSI test pin Video signal input pin Video signal input pin Video signal input pin I I 1 I ! I /
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' "`684F
l-1 I IL.
5.2
input/output
circuit
types
(1)
Input pin 1 (SP, CK, CTR, RL, SAM, CSl, CS2, MODE, TST, TSTl, TST2, TSTS, TST4, and TST5 pins) Note that SP, CK, CTP, and MODE pins do not have pull-up functions. TheTST.5 pin has the pull-down function.
Input pin Input buffer
Internal logic
(2) Input pin 2 (VA, VB, VC, Vbl , and Vb2 pins)
Input pin BBp
fnternal logic
(3) Output pin (OS1 to OS240 pins)
vcc
Sample and hold circuits --,:I:-Operational ampwer tput buffer
t
7k 4 Outpu pin
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Description 1 Functions of Functions of pin Pin functions Used as power supply pin, which is normally connected to +5.6 V. / Used as GND pin, which is connected to OV. : Used as pin for LSI testing. Must be connected to VCC. I Used as pins for LSI testing. Must be connected to VCC. : Used as pin for LSI testing. Must be connected to GND. j Used as input pin of horizontal scanning start pulse. j Used as input pin of horizontal shift clock. / Video signals are sampled in order at rise timing and fall timinglof CK. i Used as input pin of selecting video signals sampling circuits and selecting input / signals of output operational amplifiers. Used as input pin for setting the selecting of normal sampling operation j simultaneous sampling operation. or S-point
and Operations
Pin symbol vcc GND TST TSTl to TST4 TST5 SP CK CTR SAM
i For normal sampling operation, video signals are sampled in order 7 LCD drive output. For 3-point simultaneous sampling operation, video signals are sampled in order I simultaneously 3 LCD drive outputs. j For either operation, sampling signals are shifted at every rise timing and fall timing of j horfzontal shift clock of CK pin (half cfock) , and their sampling perfod is equal to the period of one clock. Used as input pin for setting the shift direction of video signals sampling sequence. ~Video signals are sampled in the order of from OS1 to OS240 when set to "H" and in tht order of from OS.240 to OS1 when set to "L". 1Used as input pins for setting of chip cascade sequence. / Set chip cascade sequence as shown in the table below. ' Cascadesequence I 1st 2nd 3rd I I ' cs1 H L H I ! ; cs2 H H L
i-
RL
CSl, cs2
MODE
Vbl Vb2 VA, VB, VC
OS1 to OS240
4th / L j L I ; For details, refer to "6-2. Operation of function" on page 7. ' Used as input pin for setting form of video signals for sampling. / By mode setting circuit, video signals are sampled and output with respect to OS1 to i OS246 in the order of VB, VA, and VC when set to "H" and in the order of VC, VB, and VA when set to `IL". / For details, refer to "6-2. Operation of function" on page 7. 1 Do not use this function in "OPEN" condition. r Used as pin for setting the bias voltage of operational amplifiers in output circuits. i Used as pin for setting bias voltage of buffers in output circuits. Used as input pins of video signals. / VB, VA, VC, ._. VB. VA, VC or VC, VB, VA. . .. VC, VB, VA are input with respect to LCD ; drive outputs OSl, OS2,OS3. ... 08238,05239,OS240 by MODE pin setting 1condition. j Used as LCD drive output pins. i All output pins discharge simultaneously at the timing of internal discharge signal and ; after discharge is completed, they output voltage corresponding to sampled video : signals.
-.
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LH1684F
6.2 Operation of function
7
(1) Examples of
cascadesequence
Horizontal Cascade Cascade scanning direction Cascade e Cascade
When RL="H"
I
I
TFT-LCD panel c`,
When RL="L"
Horizontal scanning direction e
TFT-LCD panel =>
I
--I
CSl=`H' CSP=`H'
II 1st
CSl=`L CSP=`H' Cascade sequence2nd
II
CSl=`H' CSL=`L Cascade sequence Cascade sequence
Cascade sequence
3rd
4th
(2) Video signal mode setting function With MODE pin condition, it is possible to set the fon of video signals corresponding to each output pins by selecting the mode setting circuit.
When
MODE="H"
j..
I
OS 2 OS 3
I
OS 4
I
OS 5 Output
I
OS 6 circuit
OS 1
When MODE=`L" Mode setting circuit
Output
ciicuits
LH 1684F
(3) Output circuit type The LH1684F samples video signals by the sample and hold circuits of 2 systems and outputs the voltage corresponding to the sampled data by the input switching operational amplifiers. Sample and hold circuits and output circuits are as shown in the diagram below. When CTR="H", the LH1684F samples the data to system A of the sample and hold circuits and outputs the voltage corresponding to the voltage sampled by capacitor B of system B. When CTR="L", the LH1684F samples the data to system B of the sample and hold circuits and outputs the voltage corresponding to the voltage sampled by capacitor A of system A.
System A of sample r---------------------------------. and hold circuits
.1
8
L_____________---__________________ System B of sampie and hold circuits
Therefore, it is necessary to repeat sampling operation and output operation by exchanging CTR signal to "H" and "L" for every SP signal, usually. When CTFI signal is set to "H" or "L" several times for SP signal, the same voltage is output continuously during such period. The output voltage corresponds to the data sampled by the previous sampling operation. Timing of operation is as follows.
SP
CTR I
4
System System
4
1 2
A
B --A
Sampling output 0
1
output Sampling
Sampling
output 2
3
Sampling output 2
3'
output Sampling
3' 4
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LH1684F
(4) Examples of LCD panel connection With the video signal mode setting function of (2) it is possible to connect LCD panel to the stripe pixel array panel and delta pixel array panel as shown in the following examples. (a) Example of stripe pixel array panel connection Video signals p 7 f
`1st line Sampling data 2nd line m::;:-;;:: RG B R I 1; 1d 1; 1Ii / MODE="H"
I1I 3rd line ~:]::-:::: B RG I I I
IiIi
IB IR IG /B 1 MODE="H"
R
I
IIII
Connection
of video signal input pins input pin ; VA / VB 1 VC `G/RIB
Videosignal
Video signal
Setting of video signals sampled by output circuits and MODE pin condition 1 / After 4th line lstline I 2nd line 1 3rd line OS(3n+l) j R / R j R ; R I I / OS (3n+2) G G I G G I / B OS (3n+3) B i B B j ;. U,," 1 ",," ; MODE pin setting "H" ! "H" (n=O, 1,2,. . . ,79)
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LH 1684F
(b) Examples of delta pixel array panel connection
VA VB
VC
LH1684F 0 s
1
0 s
2
0 s
3
.....................................
___--_--_
0 s
0 s
0 s
238 239 240
f Sampling data
1st line 2nd line
MODE="H"
b b IG b 1
MOD E="L"
(
+&.$I
3rd fine
___---L$g&&
MOD E="H"
Connection of video signal input pins Videosignal input pin ' VA j VB ' VC / Video signal G'R,B;
Setting of video signals sampled by output circuits and MODE pin condition 1 OS(3n+l) OS(3n+2) OS(3n+3) ! / / lstline R G B "HO, i j 2nd line B R / ; ; ! ; 3rd line R I / / After4th line B and Rare alternately selected. R and G are alternately selected.
G
B a,,"
G
"L"
MODE pin setting '
/ G and B are alternately selected. [ `L" and "H" are alternately selected. ! (n=O, 1,2,. . . ,79)
Note 1. Note 2.
Set the MODE pin condition during output discharge period. input the horizontal shift clock signal of CK pin by shifting the phase for each line according to the shift of the pixels connected to the same source bus line. ff the pixels connected to the same source bus line is shifted by half the pixels, change the clock phase 180 degrees. Clock phase must be changed during output discharge period.
LH1684F
6.3 Outline (1) of operation timing
11
Overall operation timing
Horizontal blanking period < Video signals 4 Effective display period One horizontal scanning period 0`)
> One horizontal scanning period ti+l)
.1
>
DIS
(Internal discharge signal) Sl
s240 (Internal sampling srgnals) Sampling data (j-l) output period Output diszge Sampling data 0') output period Output diszrge Sampling data (j+l) output period
OS1 to OS240 (LCD drive outputs) Output diszge
Video signals of one horizontal scanning period are sampied into the sampleand hold circuits at the timing of the internal sampling pulses of each output circuits, outputs are discharged once on the GND level by the internal discharge signal, and data corresponding to the sampled data are output. This discharge operation is performed simultaneously for all output pins.
(2) Timing of output discharge and video signal sampling The output discharge period (period "H" of the internal discharge signal DIS) is after3 cycles of clock CK from the "H" period of start pulse SPD. Therefore, the output discharge period is almost the sameperiod as the "H" period of start pulse SPD. lfthe normal sampling operation and cascade sequence is lst, the video signal sampling (internal sampling signalSn) is started after 15 cycles of clock CK following the fall of start pulse SPD. CK SP [
DIS c--Output discharge- period Sl (Normal sampling operation, cascade sequence 1 st) Video signal sampling start
LH 1684F
6.4 Timing (1) When chart for normal CSl="H", sampling operation
12
RL="H",
and CS2="H"
j si39 S240 (Internal samplrng signals) i
OS1 to OS240
Sampling data output period (2) When RL="H",
.
' Output discharge period ! Sampling data output period
CSl ="L", and CS2="H"
S240 (Internal samplrng signals);
OS1 to OS240 Sampling data output period - ' Output discharge period ! Sampling data output period
LHI 684F
13
(3)
When CK SP DIS
RL="H",
CSl ="H", and CS2="L"
s240 (Internal sampltng slgnatsj /
OS1 to OS240 Sampling data output period ' Output discharge period !Sampling data output period
(4)
When
RL="H",
CSl="L",
and CS2="L"
DIS (Internal discharge signal) ; Sl s2
si39 s240 (Internal sampling slgnaa) i
OS1 to OS240 Sampling data output period ' Output discharge period ' Sampling data output period
LH 1684F
When RL="L", CSl="H", and CS;Z="H"
14
DIS
Sl (Internal sampling slgnais) ;
OS1 to OS240 Sampling data output period (6) When RL="L", CSl="L", ' Output discharge period ! Sampling data output period
and CS2="H"
Sl (Internal sampling slgnaw i
OS1 to OS240 Sampling data output period ' Output discharge period ! Sampling data output period
(7)
When RL="L",
CK SP
CSl ="H", and CS2="L"
Sh Sl (Internal sampling srgnals) j
OS1 to OS240 Sampling data output period ' Output discharge period ! Sampling data output period
(8)
When RL="L",
CSl ="L",
and CS2="L"
iiternal
sampling signals) i
OS1 to OS240 Sampling data output period ' Output discharge period ' Sampling data output period
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LH 1684F
6.5 Timing chart for 3-point
(1) When RL="H", CSl="H",
16
simultaneous
and CS2="H"
sampling operation
S238 to S240 (Internal sampling srgnals)
OS1 to 240 d Sampling data output period ' Output discharge ' period Sampling data output period
(2)
When CK SP
FiL="H",
CSl="L",
and CS2="H"
S238 to S240 (Internal sampling signals)
OS1 to 240 .`4 ' Output discharge ' period Sampling data output period
Sampling data output period
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LH 1684F 17
(3)
When CK
RL="H",
CSl="H",
and CS2="L"
S4 to S6 1j 5135 to S237 S238 to 5240 (Internal sampling slgnars)
OS1 to 240
u -I
Sampling data output period (4) When CK SP DIS (Internal discharge signal) Sl to 53 S4 to S6 RL="H", CSl="L",
' Output discharge ! period and CS2="L"
Sampling data output period
S235 to S237 S238 to 5240 (Internal samplrng srgnay
OS1 to 240
.`I
Sampling data output period
' Output discharge r period
Sampling data output period
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LH1684F
(5)
When CK SP DIS
FiL="L",
CSl="H",
and CS2="H"
S240 to S238 S237 to 5235
S6 to S4
, I
s3 to Sl (Internal sampling signals)
/
OS1 to 240
-I-
Sampling data output period (6) When RL="L", CSl="L",
Output discharge ! period and CS2="H"
Sampling data output period
DIS (Internal discharge signal)
5237 to S235
S&OS4 s3 to Sl (Internal sampling signals)
OS1 to 240 Sampling data output period
Sampling data output period
' Output discharge ! period
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LHI 684F 19
(7)
When CK SP DIS
RL="L",
CSl ="H", and CS2="L"
s3 to Sl (Internal sampilng slgnats)
OS1 to 240
1
Sampling data output period (8) When RL="L",
' Output discharge ! period
Sampling data output period
CSl ="L", and CS2="L"
DIS (Internal discharge signal)
OS1 to 240
Sampling data output period
' Output discharge ' period
Sampling data output period
LH1684F
6.6 Precautions (1) Setting of external voltage of Vbl and Vb2 pins The LHl684Fdoes not have the biasvoltage setting circuit forthe output operational amplifiers and the output buffers. Therefore it is necessary to input the suitable voltage to Vbl pin and Vb2 pin. Set the voltage value to an optimum value in the range of Vcc to GND as shown in the diagram below, fully evaluating the current consumption, picture quality, etc. (Example of biascircuit)
20
t----r>
Vbl, Vb2
Set the resistance to Rl +R2=50 kfI
(2) Setting of Input pins Since 6 pins of SP, CK, CTR, MODE, Vbl , and Vb2 of the input pins are not pulled up or pulled down in the LSI, never use these 6 pins in the "OPEN" condition. Since VA, VB, and VC pins are for inputting video signals, necessary video signals must be input always. Except VA, VB, VC, Vbl , Vb2, SP, CK, CTR, and MODE, all other input pins are pulled up or pulled down in the LSI. However,because of preventing malfunction due to noise, etc., avoid using the "OPEN" condition whenever possible, and set to "H" level or "L"level.
(3) Input video signals Input video signalsare target for analog signals (continuous signals). The input band of video signals is applicable up to the maximumof 10 MHz.
(4) Bypass capacitor lfthe noise of alogicsystem is superposed on analog circuits such as the sample and hold circuits, analog characteristics (such as output voltage deviation and dynamic range,etc.) may deteriorate. Forthis reason, insert bypass capacits or of about 1 pF between VCC and GND. Fully evaluate and determine the value of bypass capacits orwith actually mounted on the LCD panel.
L
SHARI=
I H1684F
7. Absolute I Maximum Ratings 1
21
Parameter Supply voltage Input voltage
/ Symbol / / vcc
VINCC
Condition
i
Rating -0.3to+7.0 : j
Unit / V v "c / I I /
I I
Ta=+25 "c /
Ta=+25 "c j -0.3toVcc+0.3 1 -45to+125
j Storage temperature /
Tstg /
Note:Standard voltage is GND (0 V).
8. Recommended Operating Conditions
1
I
I
Parameter Supply voltage Input voltage
i Symbol ' / j vcc
VINCC
Condition
/
Rating +4.5to+5.5 0 to ucc -3Oto+85
; Unit / i : : u v "c j I /
: 1 / ! j
I
9. 9.1 Electrical
/ Operating temperature i
Topr
Note:Standard voltage is GND (0 V).
Characteristics
DC characteristics
Parameter Input "L" voltage Input "H" voltage Input "L" current Input "H" current Dynamic range Current consumption
/ Measuring / !Symboli condition /
1 j VIL `/IH ) / vIN=ov
I MIN /
/
TYP
j i
MAX vcc 1.0
Unit 1 Applicable pin ! U / Pins1,2,and3' j I / PA / Pinsl,and3 PA j
1 ILL 1
0 i / 0.7vcc;
I 0.3vcc !
v
/ I
1
1111 1 llL.2 /
lH1 / I
j I
i1
j I /
~
/ I
1 50.0
j ,b:",
Pins 2
Pinspil,(sa3nd2 j
/
I 1
!
viN=vCC
j
j
III-I2 )
UPP /
I
/
0.5
1
/vcc-0.5 j j 50.0 6.0
u
/ '
VA,VB,VC vcc
! I /
! Output voltage deviation 1 VOD / (Condition 1); ) ICC 1 (Condition 2)j
j mV ( OS1 toOS240 j mA 1
Unless otherwise specified, GND=O V, Ubl =Vb2=2.0 U, Ta=-30 to +85 "C. [Applicable pins] (Pin 1) Applicable to CK, CTR, SP, and MODE pins. (Pin 2) Applicable to RL, CSl , CS2, SAM, TST, and TSTl to 4 pins. (Pin 3) Applicable toTST5 pin. [Measuring condition] (Condition 1) SP signal : Cycle tSP= 63.5 ps, "H' period width twHP = 5.0 JLS CTR signal : Cycle tCTR = 127.0 ps, `H" period width tWHCT = 63.5 ps Change from "H" to "L" and vice versa during "H" period of SP signal. CK signal : Frequency fCK = 10.0 MHz Pin to be set to 2.0 V : Vbl , Vb2 Pin to be set to GND : TST5 UA=VB=UC=0.5 U to Ucc-0.5 U Connect all other pins to Vcc. Difference between the output voltage mean value of all OS output pins in the chip and the output voltage of each OS output pin. Ta=25 @
LHl684F
(Condition 2) SP signal : Cycle tS? = 63.5 us, "H" period width tWHP = 5.0 ps CTR signal : Cycle ~CTR = 127.0 us, "H" period width tWHcT = 63.5 us Change from "H" to "L" and vice versa during "H" period of SP signal. CK signal : Frequency fCK = 10.0 MHz Pin to be set to 2.0 V : Vbl , Vb2 Pin to be set to GND : TST5 Connect all other pins to Vcc.
22
9.2 _~
AC characteristics ! Measuring I / Symbol' condition
fCK
Parameter Clock frequency "H" level clock width "L" level clock width Clock rise time Clock fall time Dabsetuptime Data holdtime
I
:
MIN
/ )
TYP
! / , / MAX 1 Unit / Applicable pin CK
,
tWHC
i
SAM="H" SAM="H" SAM="L"
j 40.0 / 90.0 I 40.0 i I 1 / / 30.0 ; 30.0 0.5 I I I 0.5 5.0 90.0
1 1 ! j I I / / i ! / / I /
1
j / I / I ! / 10.0 : 35.0 / 10.0 j 35.0 I I / / / i 1.0 1 0.7 1 2.0
1.5
j SAM="L'
j tWLC :
j ns I , ns / ns / ns / ns j ns / ns j ns ns j ns
j / I j CK, SP j
I , / 1 I
/ trc
trC
j SAM="H" SAM="L" j SAM="H" j SAM="L" j
/ / j
I
tsu tH
tsup tHP
tWHP
/ SP, CTR
Pulse setup time
Pulse holdtime j "H"level pulse width / Pulse alteration time ! Output transfer delay time ,/ Output risetime Output fall time Unless otherwise / /
;
trfP
tdl tm
I
; Gondition)l
/P /psj ) pS / ps j / ps 1 ps
I 1 / SP CTR SP ~ ' j : ,
ps _I OS1 toos240 j OS1 toos240 /
tr
tf
j
:
j
t I
/ /
3.0 2.0
(
1.0
specified, GND=O V, Vbl =Vb2=2.0
V, Ta=-30 to +85"C.
[Measuring condition] (Condition) SP signal : Cycle tsP = 63.5 ps, "H" period width tWHP = 5.0 ps CTR signal : Cycle tCTR = 127.0 ps, "H" period width twHCT = 63.5 ps Change from "H" to "L" and vice versa during "H" period of S P signal. CK signal : Frequency fcK = 10.0 MHz Pin to be set to 2.0 V : Vbl , Vb2 Pin to be set to GND : TST5 Connect all other pins to Vcc. Capacity of output load CL=~ 5OpF
LH 1684F
9.3 Timing diagram
trC, tWHC >-4 tic tWLC F
23
CK
tWHP
CTR I
tdl
OS1 to OS240
SHARP
LHI 684F
10. Example of System "aA r Configuration
24
: ;R +g b' 4 I I ) t-i
LrR SP ac LL $ (D
osao0%-S0S238; : i i
"al
i&E fj VA VB vc SAM TST TSTl to 1 TST5
OS3 OS2 OS1 -
m
4 vcc
MODE o( SP
Controller
z
LH1684F
11. Example of Typical Characteristics
25
Parameter Basic gate propagation delay time
/ / I I
Conditions GND=O V,Vcc=+5.0 * Ta=+25 @ V,
1 MIN 1 TYP I MAX / Unit ' I I'Oi In=
LH1684F
12. P.4CKXGE AND PACKING SPECIFICATION 1. Package Outline Specification Refer to drawing No. SPN4701-00 2. Markings The meanings of the device code printed on each tape carrier package are as follows. (1) Date code (example) : ---- 3 8 D 0 5 a) b) c) d) a) denotes the last figure of Arino Domini (of production) b) denotes the week (of production) c) denotes factory code (of production) d) denotes the number of times of alteration 3. Packing Specifications
26
3-2 Packing Form * Specification of label a) Tape carrier package(TCP) is wound on a reel with separator and the ends of them are fixed with adhesive tape. b) A label indicating production name, lot no. TYPE Production name and quantity is stuck on one side of the reel. Lot No: c) The reel and silica gel is put in a laminated aluminium bag. Nitrogen gas is enclosed in QUANTITY Quantity the bag and the bag is sealed. The same label(b) is affixed to the bag. The bag is put LQT(DATE) Shipping date in a carton and the same label(b) is affixed to one side of the inner carton. d) 5 inner cartons are put in an outer carton and the same label(b) is affixed to one side of the outer carton. 3-3 Other (1) The length of the TCP is typically 40 m per reel, but this may change in accordance with the inventory quantity. (2) Faulty devices is conpletely punched out at the part of the device. (3) The maximum number of continuous faulty devices is 9.
I
ISSUE ISSUE 4 DATE NUMBER AUG H8801 28.1996 APPROVE CHECK DESIGN
(NO-W
S/C NUMBER
SHARP
LH1684F
4. Cautions concerning handling. Althrough the strength of the device has been verified in accodance with the test method shown below, do not subject the resin parts or the slit terminals to any excessive bending or pressure. 27
Indicate as moment M. M=FXL (N-m) M=1.47X 10e3 N*m MAX. (for both + B and - 0)
5. Cautions concerning stora,oe. - When storing the product, it is recommended that it be left in its shipping package. After the seal of the packin,0 bag has been broken, store the products in a nitrogen atmosphere. * Strage conditions Straoe state Straoe conditions humidity : 80% RH or less. ..Unopened(less than 60 davs) Temperature: 5 to 30C; _____._-_-....____-_-..------------.-. .. . . . . . ..-.-..-.-..---...---.-..`.....----.---..-.----..-.--.--......-. After seal of broken Room temperature, dry nitrogen atomosphere. * Don't store in a location exposed to corrosive gas or excessive dust. - Don't store in a location exposed to direct sunlight or subject to sharp changes in temperature. * Don't store the product such that it subjected to an excessive load weight, such as by stacking. * Deterioration of the plating may occor after long-term storage, so special` care is required. It is recommended that the products be inspected before use. 6. Other cautions. - Immediately after opening the moisture-proof packing, the mesurement will shrink slightly. In oder to return the mesurements to those shown in the drawing, it is nessesary to store the product for at least 48 hours at a temperature of 20' to 25C and humidity of 50 to 60%.
SliARf=
LH1684F
7. External appearance inspection ion of the rsternal aopearance of the packare Item I. Exposure of the inner lea and device holes Insoection standards . Faulty if.the chip or inner leads are completely exposed. . Faulty if the device holes are not completely filled with resin. ' *Faulty if there are air bubbles extending as far as the suaface of the chip. *Faulty if there are air bubbles at the inner leads. -Faulty if the area of the seal resin area exceeds the specifications. *Faulty if the thickness of the device exceeds the specifications. `Faulty if there is anything adhering to the tin plating. `Faulty if any resin or forein matter adhered to the copper pattern is wider than the width of the pattern. (If the forein matter is easily moved, it is not a cause for concern.) Faulty if there are any cracks in the chip. Faulty if there is any chipping in the underside of the chip that is lager than one-half the thickness of the chip. Faulty if adherance of the resin to the underside of the chip that causes the thickness of the device exceed the specifications. Faulty if there are any scratches exposing the sustrate (chip, pattern. or inner leads) at the seal resin. Faulty if there are any scratches extending as far as the copper foil at the sorder resists. Faulty if there are any cracks or chipping at the perforations. FdUky if the pattern overhanging the slits is markedly deformed Faulty if the tin plating is markedly discolored. Faulty if the cover coating is markedly discolored. Faulty if the markings are illegible. Faulty if the width of the output lead is reduced to less than one-half of the standard. Faulty if copper foil remnants reduce the clearanc between the output leads to less than two-thirds o the standards.
FdUlty
28
e shown below. Remarks t 1 Faulty
2. Air bubbles
3. Seal resin area &. Seal resin thickness 5. Adherance of resin or foreign matter except the seal resin area.
Jpperside: 16.5 X 5.2 mmMAX Jnderside: 16.5 X5.2 mmMAX Upperside:0.30 mmMAX Underside:0.75 mmMAX Total thickness: 1.20 mmMAX
i. Undrside of the chip
T/ZMAX f
Faulty
`. Scratches, cracks and chipping in the tape carrie
Creased n Faulty
L Pattern deformation 9. Discoloration
0. Markings 1. Missing parts of output leads
12. Other
if there is any warping, twisting. bending, etc.. of the tape that would impair use. Faulty if there are no indication holes at the noneffective indication holes.
SHARI=
LH 1684F
29
SPECIFICATION
OF
LABEL
LOTCDATE)
SHIPPNIG
DATE
REEL A d405,
`IZE B
INNER
CARTON L
DATE
AUG.
31. mm
1995
T1TLE DESIGN
420
4-20
UNIT
APROVE
REEL AND INNER OF TCP PACKING KPN
ENGNEERING
CARTON
C
.TERIAL ANTI-STATIC TREATED
0127 36
PLASTIC
SIZE
w
CHECK
DRAWINGNo. ASSEMBLY
023
H
MATERIAL CARDBOARD
50
/q, j&...??k
DEPT.
SHARP
CORPORATION
SliARP I
LH1684F
30
I
LAM1 NATED
BAG
PACKING
VIEW
OF
SHARP
LH1684F
31
FL
LABEL
OUTER
CARTON
IC GROUP SHARP CORI `ORATION
RAWING
NO
I
LH1684F
NOTES: ANTI-STATIC TREATED 1. REEL WINDING PATTERNS I DE
32
PLASTIC
[24.5&E. **.O(GOOD DEVICE HOLE) 0.6CSL) I,. 909(SL) I
L)l
1,
909(SL) I
I
0. S(SL)
VII
22. aksL)
YSEPARETOR . 2. RESIN AREA OF FRONT AND BACK SURFACE IS 16. 5X5. 2mmhAX). 3. E. L. MEANS ASSUMED EXCISING LINE. 4.SL MEANS DIMENSION OF PUNCHlNG HOLE AND ITS TOLERANCE IS k0. 05mm. 5. SR MEANS DIMENSION OF SOLDER RESIST AND ITS TOLERANCE IS CO. 3mm. 6. POTTING RESIN IS SL5.
0.75MAX.
CROSS
SECTION
OF
OUTPUT
LEADS
tj m
: r: RR (D * d d ,- _*----. -\
I : \ El - -_e* !EL ,Ii I 0. 4 to. 0. 6 to. 02 02 \ \
I
OUT
LINE
DRAWING
OF

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